[PATCH] D96075: [PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store Implementation

Amy Kwan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 22 19:17:45 PDT 2021


amyk updated this revision to Diff 339842.
amyk added a comment.

- Rebase patch
- Address review comment made by Stefan involving `plfs` and `pstxsd` using two registers such as `pstxsd v2, r3(r3), 0` (despite being a prefixed DForm instruction) instead of a register and an immediate. This was caused by the pattern for these instructions being written incorrectly. The patterns have been updated accordingly so the prefixed instructions use a register and an immediate.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96075/new/

https://reviews.llvm.org/D96075

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
  llvm/test/CodeGen/PowerPC/f128_ldst.ll
  llvm/test/CodeGen/PowerPC/int128_ldst.ll
  llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/pcrel_ldst.ll
  llvm/test/CodeGen/PowerPC/prefixed-ld-st.ll
  llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-float-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
  llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
  llvm/test/CodeGen/PowerPC/vector-ldst.ll

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