[PATCH] D99812: [PowerPC] [GlobalISel] Implementation of formal arguments lowering in the IRTranslator for the PPC backend

[Anshil Gandhi via Phabricator via llvm-commits]

gandhi21299 updated this revision to Diff 339822.
gandhi21299 marked an inline comment as done.
gandhi21299 added a comment.

- Frame Index is now built based on whether the machine is 32-bit or 64-bit


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99812/new/

https://reviews.llvm.org/D99812

Files:
  llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp


Index: llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
+++ llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
@@ -85,7 +85,7 @@
     // If we are copying the value from a physical register with the
     // size larger than the size of the value itself - build the copy
     // of the phys reg first and then build the truncation of that copy.
-    // If LocSize and ValSize are not equal we expect this to be handled 
+    // If LocSize and ValSize are not equal we expect this to be handled
     // in SExt/ZExt/AExt case.
     unsigned PhysRegSize =
         MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
@@ -148,7 +148,7 @@
   MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
 
   // Build frame index instruction based on whether the machine
-  // is 64-bit or 32-bit 
+  // is 64-bit or 32-bit
   MachineInstrBuilder AddrReg;
   if (MIRBuilder.getMF().getSubtarget<PPCSubtarget>().isPPC64())
     AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);


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