[PATCH] D101104: [X86][AVX] foldShuffleOfHorizOp - don't attempt to handle 256-bit X86ISD::VBROADCAST (PR49971)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel, wristow, tstellar.
Herald added subscribers: pengfei, hiraditya.
RKSimon requested review of this revision.
Herald added a project: LLVM.

NOTE: This is for the 12.x release branch ONLY

Minimal patch to avoid the issue encountered in PR49971 (it's already been dealt with in trunk through a larger refactor that can't be easily merged).

Bail for non-128-bit vector broadcasts of (F)HADD/SUB ops - the existing logic doesn't correctly deal with the fact that the broadcast will splat across the 128-bit lanes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101104

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/horizontal-shuffle-3.ll


Index: llvm/test/CodeGen/X86/horizontal-shuffle-3.ll
===================================================================
--- llvm/test/CodeGen/X86/horizontal-shuffle-3.ll
+++ llvm/test/CodeGen/X86/horizontal-shuffle-3.ll
@@ -98,6 +98,17 @@
   ret <8 x i32> %7
 }
 
+define <4 x double> @PR49971(<4 x double> %0) {
+; CHECK-LABEL: PR49971:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vbroadcastsd %xmm0, %ymm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %2 = tail call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %0, <4 x double> %0)
+  %3 = shufflevector <4 x double> %2, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  ret <4 x double> %3
+}
+
 declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>)
 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>)
 declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -37889,6 +37889,8 @@
   // replicating low and high halves (and without changing the type/length of
   // the vector), we don't need the shuffle.
   if (Opcode == X86ISD::MOVDDUP || Opcode == X86ISD::VBROADCAST) {
+    if (Opcode == X86ISD::VBROADCAST && !VT.is128BitVector())
+      return SDValue();
     if (HOp.getScalarValueSizeInBits() == 64 && HOp.getValueType() == VT) {
       // movddup (hadd X, X) --> hadd X, X
       // broadcast (extract_vec_elt (hadd X, X), 0) --> hadd X, X


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