[PATCH] D101002: [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32.

[Craig Topper via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG77f14c96e53a: [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D101002?vs=339412&id=339692#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101002/new/

https://reviews.llvm.org/D101002

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

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