[llvm] 528ee16 - [AArch64] Block tryCombineToBSL combines for vectors wider than NEON

[Joe Ellis via llvm-commits]

Author: Joe Ellis
Date: 2021-04-22T15:09:13Z
New Revision: 528ee161c9474ce986de13d2e86a970c2074a991

URL: https://github.com/llvm/llvm-project/commit/528ee161c9474ce986de13d2e86a970c2074a991
DIFF: https://github.com/llvm/llvm-project/commit/528ee161c9474ce986de13d2e86a970c2074a991.diff

LOG: [AArch64] Block tryCombineToBSL combines for vectors wider than NEON

There are no patterns for the AArch64ISD::BSP ISD node for anything
other than NEON vectors at the moment. As a result, if we hit these
combines for vectors wider than a NEON vector (such as what we might get
with fixed length SVE) we will fail to lower.

This patch simply prevents us from attempting the combines if the input
vector type is too wide.

Reviewed By: peterwaller-arm

Differential Revision: https://reviews.llvm.org/D100961

Added: 
    llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b0475549ee09..87a0361d1bc1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12592,6 +12592,11 @@ static SDValue tryCombineToBSL(SDNode *N,
   if (!VT.isVector())
     return SDValue();
 
+  // The combining code currently only works for NEON vectors. In particular,
+  // it does not work for SVE when dealing with vectors wider than 128 bits.
+  if (!VT.is64BitVector() && !VT.is128BitVector())
+    return SDValue();
+
   SDValue N0 = N->getOperand(0);
   if (N0.getOpcode() != ISD::AND)
     return SDValue();

diff  --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
new file mode 100644
index 000000000000..c874a8ee501d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
@@ -0,0 +1,29 @@
+; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
+
+target triple = "aarch64"
+
+;
+; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
+;       don't currently expect the code below to lower to BSL/BIT/BIF. Once
+;       this is implemented, this test will be fleshed out.
+;
+
+define <8 x i32> @fixed_bitselect_v8i32(<8 x i32>* %pre_cond_ptr, <8 x i32>* %left_ptr, <8 x i32>* %right_ptr) #0 {
+; CHECK-LABEL: fixed_bitselect_v8i32:
+; CHECK-NOT:     bsl {{.*}}, {{.*}}, {{.*}}
+; CHECK-NOT:     bit {{.*}}, {{.*}}, {{.*}}
+; CHECK-NOT:     bif {{.*}}, {{.*}}, {{.*}}
+; CHECK:         ret
+  %pre_cond = load <8 x i32>, <8 x i32>* %pre_cond_ptr
+  %left = load <8 x i32>, <8 x i32>* %left_ptr
+  %right = load <8 x i32>, <8 x i32>* %right_ptr
+
+  %neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
+  %min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+  %left_bits_0 = and <8 x i32> %neg_cond, %left
+  %right_bits_0 = and <8 x i32> %min_cond, %right
+  %bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
+  ret <8 x i32> %bsl0000
+}
+
+attributes #0 = { "target-features"="+sve" }