[PATCH] D101062: [AArch64][SVE] Better utilisation of immediate forms for bitwise intrinsics

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
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When using a predicated bitwise intrinsic with an immediate operand, if the
predicate used is all lanes active, use a unpredicated immediate form of
the instruction.

This also includes a new complex isel pattern which allows matching an
all active predicate when the types are different but the predicate is a
superset of the type being used. For example, to allow a b8 ptrue for a
b32 predicate operand.

Co-authored-by: Paul Walker <paul.walker at arm.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101062

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll

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