[PATCH] D100812: [DAGCombiner] Allow operand of step_vector to be negative.

Wed Apr 21 20:25:55 PDT 2021

craig.topper added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/rvv/stepvector.ll:277
 ; RV32-NEXT:    csrr a0, vlenb
-; RV32-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; RV32-NEXT:    vmv.v.x v8, a0
-; RV32-NEXT:    addi a0, zero, 32
-; RV32-NEXT:    vsll.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vx v16, v8, a0
+; RV32-NEXT:    srai a1, a0, 31
+; RV32-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
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junparser wrote:
> junparser wrote:
> > frasercrmck wrote:
> > > This is definitely a regression so I think we need to see what's going on here. The split-vector legalization will be causing this. Perhaps because it's still zero-extending there?
> > This is caused by  SplitVecRes_STEP_VECTOR which changes getZExtOrTrunc to getSExtOrTrunc, we may need check whether stepval is isNonNegative.
> @frasercrmck  still keep this issue open.
Does f6d8cf7798440f303d5a273999e6647cbe795ac6 make this code better?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100812/new/

https://reviews.llvm.org/D100812