[PATCH] D101002: [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, rogfer01, evandro, HsiangKai, khchen, arcbbb.
Herald added subscribers: StephenFan, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
Herald added a project: LLVM.

Rather than doing splatting each separately and doing bit manipulation
to merge them in the vector domain, copy the data to the stack
and splat it using a strided load with x0 stride. At least on
some implementations this vector load is optimized to not do
a load for each element.

This is equivalent to how we move i64 to f64 on RV32.

I've only implemented this for the intrinsic fallbacks in this
patch. I think we do similar splatting/shifting/oring in other
places. If this is approved, I'll refactor the others to share
the code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101002

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D101002.339412.patch
Type: text/x-patch
Size: 333228 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210421/ba5a0222/attachment-0001.bin>