[PATCH] D100803: [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll:51
 ; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    addi a3, zero, 5
-; LMULMAX8-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.s.x v0, a3
-; LMULMAX8-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX8-RV32-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
 ; LMULMAX8-RV32-NEXT:    vmv.v.x v25, a2
----------------
craig.topper wrote:
> This is a regression.
Andrew Waterman's advice at least for us was to use stores and a strided load with x0 stride to splat SEW=64 on RV32. This is analogous to the sequence for loading a double precision value from integer data on RV32. Should we use that instead of being clever with shifts/ors?


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  https://reviews.llvm.org/D100803/new/

https://reviews.llvm.org/D100803