[PATCH] D100435: [ARM] Transforming memset to Tail predicated Loop

[Malhar via Phabricator via llvm-commits]

malharJ added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp:296
+      Src = DAG.getZExtOrTrunc(Src, dl, MVT::i32);
+      Src = DAG.getNode(ARMISD::VDUP, dl, DAG.getVTList(MVT::v16i8), Src);
+      return DAG.getNode(ARMISD::MEMSETLOOP, dl, MVT::Other, Chain, Dst, Src.getValue(0),
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dmgreen wrote:
> It's best to create a shuffle vector or build vector, not a ARMISD::VDUP directly. That may optimize better in places.
> 
> Is the input always an i8?
I've made this update with a build vector. Have 2 minor queries:

- Why would shuffle vector be appropriate here (given that all we want to create is a vector of constants) ?

- Even though I'm not utilising vdup directly, just to understand better, why would the input need to be i8 to generate a v16i8 vector ... can the vector not be generated by a i32 source register ?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100435/new/

https://reviews.llvm.org/D100435