[PATCH] D100961: [AArch64] Block tryCombineToBSL combines for vectors wider than NEON

[Joe Ellis via Phabricator via llvm-commits]

joechrisellis created this revision.
joechrisellis added reviewers: peterwaller-arm, DavidTruby, bsmith.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
joechrisellis requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

There are no patterns for the AArch64ISD::BSP ISD node for anything
other than NEON vectors at the moment. As a result, if we hit these
combines for vectors wider than a NEON vector (such as what we might get
with fixed length SVE) we will fail to lower.

This patch simply prevents us from attempting the combines if the input
vector type is too wide.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100961

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll


Index: llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
@@ -0,0 +1,29 @@
+; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
+
+target triple = "aarch64"
+
+;
+; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
+;       don't currently expect the code below to lower to BSL/BIT/BIF. Once
+;       this is implemented, this test will be fleshed out.
+;
+
+define <8 x i32> @fixed_bitselect_v8i32(<8 x i32>* %pre_cond_ptr, <8 x i32>* %left_ptr, <8 x i32>* %right_ptr) #0 {
+; CHECK-LABEL: fixed_bitselect_v8i32:
+; CHECK-NOT:     bsl {{.*}}, {{.*}}, {{.*}}
+; CHECK-NOT:     bit {{.*}}, {{.*}}, {{.*}}
+; CHECK-NOT:     bif {{.*}}, {{.*}}, {{.*}}
+; CHECK:         ret
+  %pre_cond = load <8 x i32>, <8 x i32>* %pre_cond_ptr
+  %left = load <8 x i32>, <8 x i32>* %left_ptr
+  %right = load <8 x i32>, <8 x i32>* %right_ptr
+
+  %neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
+  %min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+  %left_bits_0 = and <8 x i32> %neg_cond, %left
+  %right_bits_0 = and <8 x i32> %min_cond, %right
+  %bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
+  ret <8 x i32> %bsl0000
+}
+
+attributes #0 = { "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12574,6 +12574,11 @@
   if (!VT.isVector())
     return SDValue();
 
+  // The combining code currently only works for NEON vectors. In particular,
+  // it does not work for SVE when dealing with vectors wider than 128 bits.
+  if (!VT.is64BitVector() && !VT.is128BitVector())
+    return SDValue();
+
   SDValue N0 = N->getOperand(0);
   if (N0.getOpcode() != ISD::AND)
     return SDValue();


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