[llvm] 2f69975 - [PhaseOrdering] Add test case for PR45682

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-04-21T15:07:00+01:00
New Revision: 2f69975683f5b6ea7df79f335f96b889a4bddecd

URL: https://github.com/llvm/llvm-project/commit/2f69975683f5b6ea7df79f335f96b889a4bddecd
DIFF: https://github.com/llvm/llvm-project/commit/2f69975683f5b6ea7df79f335f96b889a4bddecd.diff

LOG: [PhaseOrdering] Add test case for PR45682

Ensures that the correct sequence of simplifycfg/instcombine/sroa reduce the IR to just a icmp+assume (which will be dropped in backend)

Added: 
    llvm/test/Transforms/PhaseOrdering/pr45682.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/PhaseOrdering/pr45682.ll b/llvm/test/Transforms/PhaseOrdering/pr45682.ll
new file mode 100644
index 0000000000000..564f86061034a
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/pr45682.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O3 -S < %s                    | FileCheck %s
+; RUN: opt -passes='default<O3>' -S < %s  | FileCheck %s
+
+define void @PR45682(i32 %x, i32 %y) {
+; CHECK-LABEL: @PR45682(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[Y:%.*]], 0
+; CHECK-NEXT:    tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %x.addr = alloca i32, align 4
+  %y.addr = alloca i32, align 4
+  store i32 %x, i32* %x.addr, align 4
+  store i32 %y, i32* %y.addr, align 4
+  %0 = load i32, i32* %y.addr, align 4
+  %cmp = icmp sgt i32 %0, 0
+  call void @llvm.assume(i1 %cmp)
+  %1 = load i32, i32* %y.addr, align 4
+  %2 = load i32, i32* %x.addr, align 4
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* %x.addr, align 4
+  %3 = load i32, i32* %x.addr, align 4
+  %cmp1 = icmp eq i32 %3, -2147483648
+  br i1 %cmp1, label %if.then, label %if.end
+
+if.then:
+  call void @v()
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+declare void @v()
+declare void @llvm.assume(i1)