[PATCH] D100788: [SystemZ] Support i128 inline asm operands

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa updated this revision to Diff 339177.
jonpa added a comment.
Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.

The idea per the initial patch to follow the general pattern of splitting the illegal i64 during isel and then do a fixup later was proven very cumbersome. I instead tried keeping GR128 as the regclass for the inline-asm operands which was actually simpler, even still a "ugly hack" since it had 2xGR128 for each i128 operands. Even better is to fix that problem so that SelectionDAGBuilder only builds one register operand to begin with, which is what the patch now does.

These are the needed common-code changes:

- New method: TargetLowering::getNumRegistersForInlineAsmOp(). Allow target to override default number of parts for inline-asm operands.
- splitValueIntoRegisterParts() / joinRegisterPartsIntoValue(): Add a new argument to pass the Value* of the CallInst in order to identify the case of an InlineAsm instruction.
- SelectionDAGBuilder.cpp:GetRegistersForValue(): Don't do the RegClass/type fixup for MVT::Untyped.
- SelectionDAGBuilder::visitInlineAsm(): Get the RegClass from the constraint code for MVT::Untyped.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100788/new/

https://reviews.llvm.org/D100788

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZISelLowering.h
  llvm/test/CodeGen/SystemZ/inline-asm-i128.ll

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