[llvm] c6e2aed - [AArch64] Add and update reverse mask tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 21 04:11:54 PDT 2021
Author: David Green
Date: 2021-04-21T12:11:41+01:00
New Revision: c6e2aedb65e7ae2a8d63f911a5f32d9fbeeb0f62
URL: https://github.com/llvm/llvm-project/commit/c6e2aedb65e7ae2a8d63f911a5f32d9fbeeb0f62
DIFF: https://github.com/llvm/llvm-project/commit/c6e2aedb65e7ae2a8d63f911a5f32d9fbeeb0f62.diff
LOG: [AArch64] Add and update reverse mask tests. NFC
Added:
llvm/test/CodeGen/AArch64/neon-reverseshuffle.patch
Modified:
llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
index c961eabc95a8..8cdaf4e2dfda 100644
--- a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
+++ b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
@@ -150,23 +150,25 @@ define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
; Verify splitvec type legalisation works as expected.
define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
-; CHECK-LABEL: reverse_v8i32:
+; CHECK-SELDAG-LABEL: reverse_v8i32:
; CHECK-SELDAG: // %bb.0:
; CHECK-SELDAG-NEXT: rev64 v1.4s, v1.4s
; CHECK-SELDAG-NEXT: rev64 v2.4s, v0.4s
; CHECK-SELDAG-NEXT: ext v0.16b, v1.16b, v1.16b, #8
; CHECK-SELDAG-NEXT: ext v1.16b, v2.16b, v2.16b, #8
; CHECK-SELDAG-NEXT: ret
+;
+; CHECK-FASTISEL-LABEL: reverse_v8i32:
; CHECK-FASTISEL: // %bb.0:
-; CHECK-FASTISEL-NEXT: sub sp, sp, #16
-; CHECK-FASTISEL-NEXT: str q1, [sp]
-; CHECK-FASTISEL-NEXT: mov v1.16b, v0.16b
-; CHECK-FASTISEL-NEXT: ldr q0, [sp]
-; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
-; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
-; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-FASTISEL-NEXT: add sp, sp, #16
+; CHECK-FASTISEL-NEXT: sub sp, sp, #16 // =16
+; CHECK-FASTISEL-NEXT: str q1, [sp] // 16-byte Folded Spill
+; CHECK-FASTISEL-NEXT: mov v1.16b, v0.16b
+; CHECK-FASTISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
+; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
+; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-FASTISEL-NEXT: add sp, sp, #16 // =16
; CHECK-FASTISEL-NEXT: ret
%res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
@@ -175,7 +177,7 @@ define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
; Verify splitvec type legalisation works as expected.
define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
-; CHECK-LABEL: reverse_v16f32:
+; CHECK-SELDAG-LABEL: reverse_v16f32:
; CHECK-SELDAG: // %bb.0:
; CHECK-SELDAG-NEXT: rev64 v3.4s, v3.4s
; CHECK-SELDAG-NEXT: rev64 v2.4s, v2.4s
@@ -186,23 +188,25 @@ define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
; CHECK-SELDAG-NEXT: ext v2.16b, v4.16b, v4.16b, #8
; CHECK-SELDAG-NEXT: ext v3.16b, v5.16b, v5.16b, #8
; CHECK-SELDAG-NEXT: ret
+;
+; CHECK-FASTISEL-LABEL: reverse_v16f32:
; CHECK-FASTISEL: // %bb.0:
-; CHECK-FASTISEL-NEXT: sub sp, sp, #32
-; CHECK-FASTISEL-NEXT: str q3, [sp, #16]
-; CHECK-FASTISEL-NEXT: str q2, [sp]
-; CHECK-FASTISEL-NEXT: mov v2.16b, v1.16b
-; CHECK-FASTISEL-NEXT: ldr q1, [sp]
-; CHECK-FASTISEL-NEXT: mov v3.16b, v0.16b
-; CHECK-FASTISEL-NEXT: ldr q0, [sp, #16]
-; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
-; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
-; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-FASTISEL-NEXT: rev64 v2.4s, v2.4s
-; CHECK-FASTISEL-NEXT: ext v2.16b, v2.16b, v2.16b, #8
-; CHECK-FASTISEL-NEXT: rev64 v3.4s, v3.4s
-; CHECK-FASTISEL-NEXT: ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-FASTISEL-NEXT: add sp, sp, #32
+; CHECK-FASTISEL-NEXT: sub sp, sp, #32 // =32
+; CHECK-FASTISEL-NEXT: str q3, [sp, #16] // 16-byte Folded Spill
+; CHECK-FASTISEL-NEXT: str q2, [sp] // 16-byte Folded Spill
+; CHECK-FASTISEL-NEXT: mov v2.16b, v1.16b
+; CHECK-FASTISEL-NEXT: ldr q1, [sp] // 16-byte Folded Reload
+; CHECK-FASTISEL-NEXT: mov v3.16b, v0.16b
+; CHECK-FASTISEL-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
+; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
+; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
+; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-FASTISEL-NEXT: rev64 v2.4s, v2.4s
+; CHECK-FASTISEL-NEXT: ext v2.16b, v2.16b, v2.16b, #8
+; CHECK-FASTISEL-NEXT: rev64 v3.4s, v3.4s
+; CHECK-FASTISEL-NEXT: ext v3.16b, v3.16b, v3.16b, #8
+; CHECK-FASTISEL-NEXT: add sp, sp, #32 // =32
; CHECK-FASTISEL-NEXT: ret
%res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
diff --git a/llvm/test/CodeGen/AArch64/neon-reverseshuffle.patch b/llvm/test/CodeGen/AArch64/neon-reverseshuffle.patch
new file mode 100644
index 000000000000..173dec742f4d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/neon-reverseshuffle.patch
@@ -0,0 +1,156 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s -verify-machineinstrs | FileCheck %s
+
+define <2 x i64> @v2i64(<2 x i64> %a) {
+; CHECK-LABEL: v2i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x i64> %V128
+}
+
+define <4 x i32> @v4i32(<4 x i32> %a) {
+; CHECK-LABEL: v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i32> %V128
+}
+
+define <2 x i32> @v2i32(<2 x i32> %a) {
+; CHECK-LABEL: v2i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <2 x i32> %a, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x i32> %V128
+}
+
+define <8 x i16> @v8i16(<8 x i16> %a) {
+; CHECK-LABEL: v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i16> %V128
+}
+
+define <8 x i16> @v8i16_2(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-LABEL: v8i16_2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v2.4h, v0.4h
+; CHECK-NEXT: rev64 v0.4h, v1.4h
+; CHECK-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i16> %V128
+}
+
+define <4 x i16> @v4i16(<4 x i16> %a) {
+; CHECK-LABEL: v4i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i16> %V128
+}
+
+define <16 x i8> @v16i8(<16 x i8> %a) {
+; CHECK-LABEL: v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .LCPI6_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x i8> %V128
+}
+
+define <16 x i8> @v16i8_2(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: v16i8_2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .LCPI7_0
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x i8> %V128
+}
+
+define <8 x i8> @v8i8(<8 x i8> %a) {
+; CHECK-LABEL: v8i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i8> %V128
+}
+
+define <2 x double> @v2f64(<2 x double> %a) {
+; CHECK-LABEL: v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x double> %V128
+}
+
+define <4 x float> @v4f32(<4 x float> %a) {
+; CHECK-LABEL: v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x float> %V128
+}
+
+define <2 x float> @v2f32(<2 x float> %a) {
+; CHECK-LABEL: v2f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <2 x float> %a, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x float> %V128
+}
+
+define <8 x half> @v8f16(<8 x half> %a) {
+; CHECK-LABEL: v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .LCPI12_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x half> %V128
+}
+
+define <4 x half> @v4f16(<4 x half> %a) {
+; CHECK-LABEL: v4f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: ret
+entry:
+ %V128 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x half> %V128
+}
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