[llvm] ad0fe5d - [RISCV][MC] Mask load should not have VMConstraint.

[Zakk Chen via llvm-commits]

Author: Zakk Chen
Date: 2021-04-21T15:21:37+08:00
New Revision: ad0fe5db2fa07595cd96e1c7c422bb6ba75a351f

URL: https://github.com/llvm/llvm-project/commit/ad0fe5db2fa07595cd96e1c7c422bb6ba75a351f
DIFF: https://github.com/llvm/llvm-project/commit/ad0fe5db2fa07595cd96e1c7c422bb6ba75a351f.diff

LOG: [RISCV][MC] Mask load should not have VMConstraint.

Add a test, dest register could be v0.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D100825

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    llvm/test/MC/RISCV/rvv/load.s

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 2c0d8f2f51633..88c1c11b3546f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -88,6 +88,7 @@ class VUnitStrideLoadMask<string opcodestr>
                 (outs VR:$vd),
                 (ins GPR:$rs1), opcodestr, "$vd, (${rs1})"> {
   let vm = 1;
+  let RVVConstraint = NoConstraint;
 }
 
 // load vd, (rs1), vm

diff  --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s
index 4e670e0afe949..dc01608021314 100644
--- a/llvm/test/MC/RISCV/rvv/load.s
+++ b/llvm/test/MC/RISCV/rvv/load.s
@@ -8,6 +8,12 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+vle1.v v0, (a0)
+# CHECK-INST: vle1.v v0, (a0)
+# CHECK-ENCODING: [0x07,0x00,0xb5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 00 b5 02 <unknown>
+
 vle1.v v8, (a0)
 # CHECK-INST: vle1.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x02]