[PATCH] D100823: [RISCV] Implement the pseudo compare builtin.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Thinking about this more, I'd like to consider doing this in the backend specifically for the compares for a few reasons.

-vmsgt(u).vv intrinsic already selects vmslt(u).vv with swapped operands in the backend. This was needed for SEW=64 on RV32.
-Inconsistent that some compare IR intrinsics accept vector or scalar second argument, but some only support scalar.
-We can probably generate better code for masked vmsge(u).vx if we defer expansion to post register allocation.
-Unifies the compare intrinsic implementation in the frontend.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100823/new/

https://reviews.llvm.org/D100823