[llvm] 4e2c419 - [NFC][InstCombine] Add test for sign-extending NSW trunc (PR49543)

[Roman Lebedev via llvm-commits]

Author: Roman Lebedev
Date: 2021-04-21T00:31:45+03:00
New Revision: 4e2c4190bed7596980bf474db8c6b4ebbad97203

URL: https://github.com/llvm/llvm-project/commit/4e2c4190bed7596980bf474db8c6b4ebbad97203
DIFF: https://github.com/llvm/llvm-project/commit/4e2c4190bed7596980bf474db8c6b4ebbad97203.diff

LOG: [NFC][InstCombine] Add test for sign-extending NSW trunc (PR49543)

Added: 
    llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll b/llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll
new file mode 100644
index 000000000000..10098d946bf7
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll
@@ -0,0 +1,103 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Iff we know that trunc only chops off the sign bits,
+; and not all of them, then we can bypass said trunc
+; for the purpose of sign extension.
+
+declare void @use8(i8)
+declare void @use4(i4)
+declare void @usevec(<2 x i8>)
+
+define i16 @t0(i8 %x) {
+; CHECK-LABEL: @t0(
+; CHECK-NEXT:    [[A:%.*]] = ashr i8 [[X:%.*]], 5
+; CHECK-NEXT:    call void @use8(i8 [[A]])
+; CHECK-NEXT:    [[B:%.*]] = trunc i8 [[A]] to i4
+; CHECK-NEXT:    [[C:%.*]] = sext i4 [[B]] to i16
+; CHECK-NEXT:    ret i16 [[C]]
+;
+  %a = ashr i8 %x, 5
+  call void @use8(i8 %a)
+  %b = trunc i8 %a to i4
+  %c = sext i4 %b to i16
+  ret i16 %c
+}
+
+define i16 @t1(i8 %x) {
+; CHECK-LABEL: @t1(
+; CHECK-NEXT:    [[A:%.*]] = ashr i8 [[X:%.*]], 4
+; CHECK-NEXT:    call void @use8(i8 [[A]])
+; CHECK-NEXT:    [[B:%.*]] = trunc i8 [[A]] to i4
+; CHECK-NEXT:    [[C:%.*]] = sext i4 [[B]] to i16
+; CHECK-NEXT:    ret i16 [[C]]
+;
+  %a = ashr i8 %x, 4
+  call void @use8(i8 %a)
+  %b = trunc i8 %a to i4
+  %c = sext i4 %b to i16
+  ret i16 %c
+}
+
+; Here we don't know that %a has any sign bits from %x left
+define i16 @n2(i8 %x) {
+; CHECK-LABEL: @n2(
+; CHECK-NEXT:    [[A:%.*]] = ashr i8 [[X:%.*]], 3
+; CHECK-NEXT:    call void @use8(i8 [[A]])
+; CHECK-NEXT:    [[B:%.*]] = trunc i8 [[A]] to i4
+; CHECK-NEXT:    [[C:%.*]] = sext i4 [[B]] to i16
+; CHECK-NEXT:    ret i16 [[C]]
+;
+  %a = ashr i8 %x, 3
+  call void @use8(i8 %a)
+  %b = trunc i8 %a to i4
+  %c = sext i4 %b to i16
+  ret i16 %c
+}
+
+define <2 x i16> @t3_vec(<2 x i8> %x) {
+; CHECK-LABEL: @t3_vec(
+; CHECK-NEXT:    [[A:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 4, i8 4>
+; CHECK-NEXT:    call void @usevec(<2 x i8> [[A]])
+; CHECK-NEXT:    [[B:%.*]] = trunc <2 x i8> [[A]] to <2 x i4>
+; CHECK-NEXT:    [[C:%.*]] = sext <2 x i4> [[B]] to <2 x i16>
+; CHECK-NEXT:    ret <2 x i16> [[C]]
+;
+  %a = ashr <2 x i8> %x, <i8 4, i8 4>
+  call void @usevec(<2 x i8> %a)
+  %b = trunc <2 x i8> %a to <2 x i4>
+  %c = sext <2 x i4> %b to <2 x i16>
+  ret <2 x i16> %c
+}
+
+define <2 x i16> @t4_vec_nonsplat(<2 x i8> %x) {
+; CHECK-LABEL: @t4_vec_nonsplat(
+; CHECK-NEXT:    [[A:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 4, i8 3>
+; CHECK-NEXT:    call void @usevec(<2 x i8> [[A]])
+; CHECK-NEXT:    [[B:%.*]] = trunc <2 x i8> [[A]] to <2 x i4>
+; CHECK-NEXT:    [[C:%.*]] = sext <2 x i4> [[B]] to <2 x i16>
+; CHECK-NEXT:    ret <2 x i16> [[C]]
+;
+  %a = ashr <2 x i8> %x, <i8 4, i8 3>
+  call void @usevec(<2 x i8> %a)
+  %b = trunc <2 x i8> %a to <2 x i4>
+  %c = sext <2 x i4> %b to <2 x i16>
+  ret <2 x i16> %c
+}
+
+define i16 @t5_extrause(i8 %x) {
+; CHECK-LABEL: @t5_extrause(
+; CHECK-NEXT:    [[A:%.*]] = ashr i8 [[X:%.*]], 5
+; CHECK-NEXT:    call void @use8(i8 [[A]])
+; CHECK-NEXT:    [[B:%.*]] = trunc i8 [[A]] to i4
+; CHECK-NEXT:    call void @use4(i4 [[B]])
+; CHECK-NEXT:    [[C:%.*]] = sext i4 [[B]] to i16
+; CHECK-NEXT:    ret i16 [[C]]
+;
+  %a = ashr i8 %x, 5
+  call void @use8(i8 %a)
+  %b = trunc i8 %a to i4
+  call void @use4(i4 %b)
+  %c = sext i4 %b to i16
+  ret i16 %c
+}