[llvm] e7d8105 - [COST]Add a test for reverse shuffles cost on AArch64, NFC.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2021-04-20T10:01:14-07:00
New Revision: e7d810537385bf3790b172208b3b6c31c4bdb3fa

URL: https://github.com/llvm/llvm-project/commit/e7d810537385bf3790b172208b3b6c31c4bdb3fa
DIFF: https://github.com/llvm/llvm-project/commit/e7d810537385bf3790b172208b3b6c31c4bdb3fa.diff

LOG: [COST]Add a test for reverse shuffles cost on AArch64, NFC.

Added: 
    llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll
new file mode 100644
index 0000000000000..c23b6eff7237e
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll
@@ -0,0 +1,61 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -mtriple=aarch64--linux-gnu -cost-model -analyze | FileCheck %s
+
+;
+; Verify the cost model for reverse shuffles.
+;
+
+define void @test_vXi32(<2 x i32> %src64, <4 x i32> %src128) {
+; CHECK-LABEL: 'test_vXi32'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
+  %V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret void
+}
+
+define void @test_vXi64(<2 x i64> %src128) {
+; CHECK-LABEL: 'test_vXi64'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
+  ret void
+}
+
+define void @test_vXf32(<2 x float> %src64, <4 x float> %src128) {
+; CHECK-LABEL: 'test_vXf32'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret void
+}
+
+define void @test_vXf64(<2 x double> %src128) {
+; CHECK-LABEL: 'test_vXf64'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+  ret void
+}
+
+;
+; Tests the cost model for reverse shuffles of second operand.
+;
+
+define void @test_upper_vXf32(<2 x float> %a64, <2 x float> %b64, <4 x float> %a128, <4 x float> %b128) {
+; CHECK-LABEL: 'test_upper_vXf32'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V64 = shufflevector <2 x float> %a64, <2 x float> %b64, <2 x i32> <i32 3, i32 2>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %V128 = shufflevector <4 x float> %a128, <4 x float> %b128, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %V64 = shufflevector <2 x float> %a64, <2 x float> %b64, <2 x i32> <i32 3, i32 2>
+  %V128 = shufflevector <4 x float> %a128, <4 x float> %b128, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
+  ret void
+}