[PATCH] D100430: [AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads

[Vang Thao via Phabricator via llvm-commits]

vangthao updated this revision to Diff 338904.
vangthao added a comment.

Fix destination regiser bug in buildZExtInReg and use it for widening scalar G_ZEXTLOAD memory access.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100430/new/

https://reviews.llvm.org/D100430

Files:
  llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll

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