[llvm] 087e98a - [PhaseOrdering] Add second test case for PR36760

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-04-20T17:27:24+01:00
New Revision: 087e98aab0ac9ceebe09449348f47c1fb3b18b6d

URL: https://github.com/llvm/llvm-project/commit/087e98aab0ac9ceebe09449348f47c1fb3b18b6d
DIFF: https://github.com/llvm/llvm-project/commit/087e98aab0ac9ceebe09449348f47c1fb3b18b6d.diff

LOG: [PhaseOrdering] Add second test case for PR36760

Added: 
    

Modified: 
    llvm/test/Transforms/PhaseOrdering/pr36760.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/PhaseOrdering/pr36760.ll b/llvm/test/Transforms/PhaseOrdering/pr36760.ll
index 5f8fb9fc1143..80997dc82148 100644
--- a/llvm/test/Transforms/PhaseOrdering/pr36760.ll
+++ b/llvm/test/Transforms/PhaseOrdering/pr36760.ll
@@ -33,3 +33,36 @@ return:
   %3 = load i64, i64* %retval, align 8
   ret i64 %3
 }
+
+define i64 @PR36760_2(i64 %a) #0 {
+; CHECK-LABEL: @PR36760_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp slt i64 [[A:%.*]], -1
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[TMP0]], i64 [[A]], i64 -1
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = xor i64 [[TMP1]], -1
+; CHECK-NEXT:    ret i64 [[RETVAL_0]]
+;
+entry:
+  %retval = alloca i64, align 8
+  %a.addr = alloca i64, align 8
+  store i64 %a, i64* %a.addr, align 8
+  %0 = load i64, i64* %a.addr, align 8
+  %cmp = icmp sge i64 %0, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i64 0, i64* %retval, align 8
+  br label %return
+
+if.end:                                           ; preds = %entry
+  %1 = load i64, i64* %a.addr, align 8
+  %shr = ashr i64 %1, 63
+  %2 = load i64, i64* %a.addr, align 8
+  %xor = xor i64 %shr, %2
+  store i64 %xor, i64* %retval, align 8
+  br label %return
+
+return:                                           ; preds = %if.end, %if.then
+  %3 = load i64, i64* %retval, align 8
+  ret i64 %3
+}