[PATCH] D100803: [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2676
+
+    if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
+      int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
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I'm wondering if you could fold this optimization into `splatPartsI64WithVL`


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100803/new/

https://reviews.llvm.org/D100803