[llvm] 2a419a0 - [X86][SSE] combineX86ShuffleChain - check if we're blending with zero into already zero elements
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 20 09:10:07 PDT 2021
Author: Simon Pilgrim
Date: 2021-04-20T17:09:49+01:00
New Revision: 2a419a0b9957ebac9e11e4b43bc9fbe42a9207df
URL: https://github.com/llvm/llvm-project/commit/2a419a0b9957ebac9e11e4b43bc9fbe42a9207df
DIFF: https://github.com/llvm/llvm-project/commit/2a419a0b9957ebac9e11e4b43bc9fbe42a9207df.diff
LOG: [X86][SSE] combineX86ShuffleChain - check if we're blending with zero into already zero elements
Add a SelectionDAG::MaskedElementsAreZero helper that wraps SelectionDAG::MaskedValueIsZero testing for entirely zero vector elements
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/oddshuffles.ll
llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 7948bd3fbfdfc..61c6e3233d022 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1748,6 +1748,11 @@ class SelectionDAG {
bool MaskedValueIsZero(SDValue Op, const APInt &Mask,
const APInt &DemandedElts, unsigned Depth = 0) const;
+ /// Return true if the DemandedElts of the vector Op are all zero. We
+ /// use this predicate to simplify operations downstream.
+ bool MaskedElementsAreZero(SDValue Op, const APInt &DemandedElts,
+ unsigned Depth = 0) const;
+
/// Return true if '(Op & Mask) == Mask'.
/// Op and Mask are known to be the same type.
bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 745f8991bf794..782b9b0e5388b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2442,6 +2442,15 @@ bool SelectionDAG::MaskedValueIsZero(SDValue V, const APInt &Mask,
return Mask.isSubsetOf(computeKnownBits(V, DemandedElts, Depth).Zero);
}
+/// Return true if the DemandedElts of the vector Op are all zero. We
+/// use this predicate to simplify operations downstream.
+bool SelectionDAG::MaskedElementsAreZero(SDValue Op, const APInt &DemandedElts,
+ unsigned Depth) const {
+ unsigned BitWidth = Op.getScalarValueSizeInBits();
+ APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
+ return MaskedValueIsZero(Op, DemandedBits, DemandedElts, Depth);
+}
+
/// MaskedValueIsAllOnes - Return true if '(Op & Mask) == Mask'.
bool SelectionDAG::MaskedValueIsAllOnes(SDValue V, const APInt &Mask,
unsigned Depth) const {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8cf0bef11d2c9..8ae0df6313af3 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35677,6 +35677,15 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
}
}
+ // See if this is a blend with zero - in which case check if the zero'd
+ // elements are already zero.
+ if (isSequentialOrUndefOrZeroInRange(Mask, 0, NumMaskElts, 0)) {
+ assert(!KnownZero.isNullValue() && "Shuffle has no zero elements");
+ SDValue NewV1 = CanonicalizeShuffleInput(MaskVT, V1);
+ if (DAG.MaskedElementsAreZero(NewV1, KnownZero))
+ return DAG.getBitcast(RootVT, NewV1);
+ }
+
SDValue NewV1 = V1; // Save operand in case early exit happens.
if (matchUnaryShuffle(MaskVT, Mask, AllowFloatDomain, AllowIntDomain, NewV1,
DL, DAG, Subtarget, Shuffle, ShuffleSrcVT,
diff --git a/llvm/test/CodeGen/X86/oddshuffles.ll b/llvm/test/CodeGen/X86/oddshuffles.ll
index dad3251db0e74..7a2ec7cd0ffe5 100644
--- a/llvm/test/CodeGen/X86/oddshuffles.ll
+++ b/llvm/test/CodeGen/X86/oddshuffles.ll
@@ -2015,8 +2015,8 @@ define <16 x i32> @splat_v3i32(<3 x i32>* %ptr) {
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: vpinsrd $2, 8(%rdi), %xmm0, %xmm1
; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0],ymm0[1],ymm2[2,3,4,5,6,7]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0],ymm1[1],ymm2[2,3,4,5,6,7]
+; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,0,1]
; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4,5,6,7]
; AVX1-NEXT: retq
;
@@ -2042,8 +2042,8 @@ define <16 x i32> @splat_v3i32(<3 x i32>* %ptr) {
; XOP-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; XOP-NEXT: vpinsrd $2, 8(%rdi), %xmm0, %xmm1
; XOP-NEXT: vxorps %xmm2, %xmm2, %xmm2
-; XOP-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0],ymm0[1],ymm2[2,3,4,5,6,7]
-; XOP-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; XOP-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0],ymm1[1],ymm2[2,3,4,5,6,7]
+; XOP-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,0,1]
; XOP-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4,5,6,7]
; XOP-NEXT: retq
%1 = load <3 x i32>, <3 x i32>* %ptr, align 1
diff --git a/llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll b/llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
index cf42ed3c2612c..f2dd7af2d558b 100644
--- a/llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
+++ b/llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
@@ -3088,24 +3088,13 @@ define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_1(<2 x i64> %a
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrad $1, %xmm0
-; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq
;
-; X64-AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
-; X64-AVX1: # %bb.0:
-; X64-AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX1-NEXT: vpsrad $1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X64-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
-; X64-AVX1-NEXT: retq
-;
-; X64-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
-; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX2-NEXT: vpsrad $1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X64-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
-; X64-AVX2-NEXT: retq
+; X64-AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; X64-AVX: # %bb.0:
+; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: vpsrad $1, %xmm0, %xmm0
+; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
%t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
ret <2 x i64> %t1
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