[PATCH] D100430: [AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads

[Vang Thao via Phabricator via llvm-commits]

vangthao added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:1182
+        auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
+        auto Mask = B.buildConstant(
+            S32, APInt::getLowBitsSet(S32.getScalarSizeInBits(), MemSize));
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foad wrote:
> Use B.buildZExtInReg.
I attempted to use B.buildZExtInReg but this function creates a new virtual register as the destination instead of using MI.getOperand(0)'s register when passing it as the first argument. This is unlike buildSExtInReg which uses the first argument as the destination.


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  https://reviews.llvm.org/D100430/new/

https://reviews.llvm.org/D100430