[PATCH] D100812: [DAGCombiner] Allow operand of step_vector to be negative.

Tue Apr 20 06:58:49 PDT 2021

frasercrmck added a comment.

Hmm I just saw that D100088 <https://reviews.llvm.org/D100088> went in without anyone involved with RISC-V being on the reviewer list or notified. I think that's technically a regression since the RISC-V backend crashes on all those test cases that were added.

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Comment at: llvm/test/CodeGen/RISCV/rvv/stepvector.ll:277
 ; RV32-NEXT:    csrr a0, vlenb
-; RV32-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; RV32-NEXT:    vmv.v.x v8, a0
-; RV32-NEXT:    addi a0, zero, 32
-; RV32-NEXT:    vsll.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vx v16, v8, a0
+; RV32-NEXT:    srai a1, a0, 31
+; RV32-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
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This is definitely a regression so I think we need to see what's going on here. The split-vector legalization will be causing this. Perhaps because it's still zero-extending there?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100812/new/

https://reviews.llvm.org/D100812