[PATCH] D100847: [RISCV] Further fixes for RVV stack offset computation

Tue Apr 20 05:32:59 PDT 2021

frasercrmck added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir:154
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
+  ; CHECK:   liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
   ; CHECK:   renamable $x9 = COPY killed renamable $x13
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I should have noticed this in the earlier patch, we //were// using three registers but since `$x9` isn't a live-in to the successor block it wasn't requiring an emergency spill lot.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100847/new/

https://reviews.llvm.org/D100847