[PATCH] D100574: [RISCV] Fix missing emergency slots for scalable stack offsets

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked an inline comment as done.
frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:863
+    // For RVV, scalable stack offsets require up to two scratch registers to
+    // compute the final offset. Reserve an additional emergency spill slot.
+    if (RVVStackSize != 0) {
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HsiangKai wrote:
> What if `!isInt<11>(MFI.estimateStackSize(MF))` and `RVVStackSize != 0` occurred in the same function, do we need three or two emergency spill slot in total?
I had assumed the worst case would still be two, but I'll run some tests.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1364
+        .addReg(N, RegState::Kill)
+        .addReg(VL, RegState::Kill);
   }
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HsiangKai wrote:
> Sorry, it is my fault. We may have no need to switch the order of the operands.
> Let's keep the order to reduce the difference in the test cases.
> 
> ```
> BuildMI(MBB, II, DL, TII->get(RISCV::MUL), VL)
>     .addReg(VL, RegState::Kill)
>     .addReg(N, RegState::Kill);
> ```
Makes sense, the diff is better like this. Thanks


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  https://reviews.llvm.org/D100574/new/

https://reviews.llvm.org/D100574