[PATCH] D100702: [RISCV] Handle PseudoVRELOAD and PseudoVSPILL in getInstSizeInBytes.
Zakk Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 19 22:30:50 PDT 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd5fa71e9ecc5: [RISCV] Handle PseudoVRELOAD and PseudoVSPILL in getInstSizeInBytes. (authored by khchen).
Changed prior to commit:
https://reviews.llvm.org/D100702?vs=338300&id=338718#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D100702/new/
https://reviews.llvm.org/D100702
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -770,6 +770,33 @@
return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
*TM.getMCAsmInfo());
}
+ case RISCV::PseudoVSPILL2_M1:
+ case RISCV::PseudoVSPILL2_M2:
+ case RISCV::PseudoVSPILL2_M4:
+ case RISCV::PseudoVSPILL3_M1:
+ case RISCV::PseudoVSPILL3_M2:
+ case RISCV::PseudoVSPILL4_M1:
+ case RISCV::PseudoVSPILL4_M2:
+ case RISCV::PseudoVSPILL5_M1:
+ case RISCV::PseudoVSPILL6_M1:
+ case RISCV::PseudoVSPILL7_M1:
+ case RISCV::PseudoVSPILL8_M1:
+ case RISCV::PseudoVRELOAD2_M1:
+ case RISCV::PseudoVRELOAD2_M2:
+ case RISCV::PseudoVRELOAD2_M4:
+ case RISCV::PseudoVRELOAD3_M1:
+ case RISCV::PseudoVRELOAD3_M2:
+ case RISCV::PseudoVRELOAD4_M1:
+ case RISCV::PseudoVRELOAD4_M2:
+ case RISCV::PseudoVRELOAD5_M1:
+ case RISCV::PseudoVRELOAD6_M1:
+ case RISCV::PseudoVRELOAD7_M1:
+ case RISCV::PseudoVRELOAD8_M1: {
+ // The values are determined based on expandVSPILL and expandVRELOAD that
+ // expand the pseudos depending on NF.
+ unsigned NF = isRVVSpillForZvlsseg(Opcode)->first;
+ return 4 * (2 * NF - 1);
+ }
}
}
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