[PATCH] D100815: [RISCV] Turn splat shuffles of vector loads into strided load with stride of x0.

[Craig Topper via Phabricator via llvm-commits]

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Implementations are allowed to optimize an x0 stride to perform
less memory accesses. This is the case in SiFive cores.

No idea if this is the case in other implementations. We might
need a tuning flag for this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100815

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

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