[llvm] b7249bf - [RISCV][test] Add a new test of addition

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2021-04-20T12:11:56+08:00
New Revision: b7249bf3b5f56fcd9349b862be5aa669679998e4

URL: https://github.com/llvm/llvm-project/commit/b7249bf3b5f56fcd9349b862be5aa669679998e4
DIFF: https://github.com/llvm/llvm-project/commit/b7249bf3b5f56fcd9349b862be5aa669679998e4.diff

LOG: [RISCV][test] Add a new test of addition

Reviewed by: craig.topper

Differential Revision: https://reviews.llvm.org/D100767

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/add-imm.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/add-imm.ll b/llvm/test/CodeGen/RISCV/add-imm.ll
index 2db13eb0ba839..548a2e2579b82 100644
--- a/llvm/test/CodeGen/RISCV/add-imm.ll
+++ b/llvm/test/CodeGen/RISCV/add-imm.ll
@@ -150,6 +150,23 @@ define i32 @add32_accept(i32 %a) nounwind {
   ret i32 %1
 }
 
+define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
+; RV32I-LABEL: add32_sext_accept:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 1500
+; RV32I-NEXT:    addi a0, a0, 1499
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add32_sext_accept:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, -1097
+; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 2999
+  ret i32 %1
+}
+
 define i64 @add64_accept(i64 %a) nounwind {
 ; RV32I-LABEL: add64_accept:
 ; RV32I:       # %bb.0: