[PATCH] D100812: [DAGCombiner] Allow operand of step_vector to be negative.

[JunMa via Phabricator via llvm-commits]

junparser created this revision.
junparser added reviewers: david-arm, sdesmalen, paulwalker-arm, ctetreau, efriedma, kmclaughlin.
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It is proper to relax non-negative limitation of step_vector.

  Also this patch adds more combines for step_vector:
  (sub X, step_vector(C)) -> (add X,  step_vector(-C))


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100812

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/sve-stepvector.ll


Index: llvm/test/CodeGen/AArch64/sve-stepvector.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-stepvector.ll
+++ llvm/test/CodeGen/AArch64/sve-stepvector.ll
@@ -259,6 +259,18 @@
   ret <vscale x 8 x i8> %3
 }
 
+define <vscale x 8 x i16> @sub_stepvector_nxv8i16() {
+; CHECK-LABEL: sub_stepvector_nxv8i16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    index z0.h, #2, #-1
+; CHECK-NEXT:    ret
+entry:
+  %0 = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
+  %1 = shufflevector <vscale x 8 x i16> %0, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
+  %2 = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
+  %3 = sub <vscale x 8 x i16> %1, %2
+  ret <vscale x 8 x i16> %3
+}
 
 declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
 declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4709,8 +4709,7 @@
     assert(Operand.getValueType().bitsGE(VT.getScalarType()) &&
            "Operand type should be at least as large as the element type");
     assert(isa<ConstantSDNode>(Operand) &&
-           cast<ConstantSDNode>(Operand)->getAPIntValue().isNonNegative() &&
-           "Expected positive integer constant for STEP_VECTOR");
+           "Expected integer constant for STEP_VECTOR");
     break;
   case ISD::FREEZE:
     assert(VT == Operand.getValueType() && "Unexpected VT!");
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3544,6 +3544,14 @@
     return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
   }
 
+  // canonicalize (sub X, step_vector(C)) to (add X,  step_vector(-C))
+  if (N1.getOpcode() == ISD::STEP_VECTOR) {
+    SDValue NewStep = DAG.getConstant(-N1.getConstantOperandAPInt(0), DL,
+                                      N1.getOperand(0).getValueType());
+    return DAG.getNode(ISD::ADD, DL, VT, N0,
+                       DAG.getStepVector(SDLoc(N), VT, NewStep));
+  }
+
   // Prefer an add for more folding potential and possibly better codegen:
   // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
   if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
Index: llvm/include/llvm/CodeGen/ISDOpcodes.h
===================================================================
--- llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -594,8 +594,8 @@
 
   /// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised
   /// of a linear sequence of unsigned values starting from 0 with a step of
-  /// IMM, where IMM must be a constant positive integer value. The operation
-  /// does not support returning fixed-width vectors or non-constant operands.
+  /// IMM, where IMM must be a constant integer value. The operation does not
+  /// support returning fixed-width vectors or non-constant operands.
   /// If the sequence value exceeds the limit allowed for the element type then
   /// the values for those lanes are undefined.
   STEP_VECTOR,


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