[PATCH] D100574: [RISCV] Fix missing emergency slots for scalable stack offsets

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:863
+    // For RVV, scalable stack offsets require up to two scratch registers to
+    // compute the final offset. Reserve an additional emergency spill slot.
+    if (RVVStackSize != 0) {
----------------
What if `!isInt<11>(MFI.estimateStackSize(MF))` and `RVVStackSize != 0` occurred in the same function, do we need three or two emergency spill slot in total?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1364
+        .addReg(N, RegState::Kill)
+        .addReg(VL, RegState::Kill);
   }
----------------
Sorry, it is my fault. We may have no need to switch the order of the operands.
Let's keep the order to reduce the difference in the test cases.

```
BuildMI(MBB, II, DL, TII->get(RISCV::MUL), VL)
    .addReg(VL, RegState::Kill)
    .addReg(N, RegState::Kill);
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100574/new/

https://reviews.llvm.org/D100574