[llvm] b98807d - [CSSPGO] Exclude pseudo probes from slot index
Hongtao Yu via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 19 17:55:48 PDT 2021
Author: Hongtao Yu
Date: 2021-04-19T17:55:35-07:00
New Revision: b98807df05cb4cd728e744c3349a9dfd341f6f61
URL: https://github.com/llvm/llvm-project/commit/b98807df05cb4cd728e744c3349a9dfd341f6f61
DIFF: https://github.com/llvm/llvm-project/commit/b98807df05cb4cd728e744c3349a9dfd341f6f61.diff
LOG: [CSSPGO] Exclude pseudo probes from slot index
Pseudo probe are currently given a slot index like other regular instructions. This affects register pressure and lifetime weight computation because of enlarged lifetime length with pseudo probe instructions. As a consequence, program could get different code generated w/ and w/o pseudo probes. I'm closing the gap by excluding pseudo probes from stack index and downstream register allocation related passes.
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D100334
Added:
llvm/test/Transforms/SampleProfile/pseudo-probe-slotindex.ll
Modified:
llvm/lib/CodeGen/LexicalScopes.cpp
llvm/lib/CodeGen/LiveDebugVariables.cpp
llvm/lib/CodeGen/LiveIntervals.cpp
llvm/lib/CodeGen/LiveRangeShrink.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/lib/CodeGen/RegisterPressure.cpp
llvm/lib/CodeGen/RegisterScavenging.cpp
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/lib/CodeGen/SlotIndexes.cpp
llvm/lib/CodeGen/SplitKit.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/LexicalScopes.cpp b/llvm/lib/CodeGen/LexicalScopes.cpp
index 8139c2cbb6cde..47c19c3d8ec45 100644
--- a/llvm/lib/CodeGen/LexicalScopes.cpp
+++ b/llvm/lib/CodeGen/LexicalScopes.cpp
@@ -75,6 +75,11 @@ void LexicalScopes::extractLexicalScopes(
const MachineInstr *PrevMI = nullptr;
const DILocation *PrevDL = nullptr;
for (const auto &MInsn : MBB) {
+ // Ignore DBG_VALUE and similar instruction that do not contribute to any
+ // instruction in the output.
+ if (MInsn.isMetaInstruction())
+ continue;
+
// Check if instruction has valid location information.
const DILocation *MIDL = MInsn.getDebugLoc();
if (!MIDL) {
@@ -88,11 +93,6 @@ void LexicalScopes::extractLexicalScopes(
continue;
}
- // Ignore DBG_VALUE and similar instruction that do not contribute to any
- // instruction in the output.
- if (MInsn.isMetaInstruction())
- continue;
-
if (RangeBeginMI) {
// If we have already seen a beginning of an instruction range and
// current instruction scope does not match scope of first instruction
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index 751e4f665690f..ce898cddb791c 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -870,7 +870,7 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
MBBI != MBBE;) {
// Use the first debug instruction in the sequence to get a SlotIndex
// for following consecutive debug instructions.
- if (!MBBI->isDebugInstr()) {
+ if (!MBBI->isDebugOrPseudoInstr()) {
++MBBI;
continue;
}
@@ -891,7 +891,7 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
Changed = true;
} else
++MBBI;
- } while (MBBI != MBBE && MBBI->isDebugInstr());
+ } while (MBBI != MBBE && MBBI->isDebugOrPseudoInstr());
}
}
return Changed;
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 7d0e0d90cebcd..c038ba9430121 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -1484,7 +1484,7 @@ class LiveIntervals::HMEditor {
MachineBasicBlock::iterator Begin = MBB->begin();
while (MII != Begin) {
- if ((--MII)->isDebugInstr())
+ if ((--MII)->isDebugOrPseudoInstr())
continue;
SlotIndex Idx = Indexes->getInstructionIndex(*MII);
@@ -1579,7 +1579,7 @@ void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
continue;
SlotIndex instrIdx = getInstructionIndex(MI);
@@ -1676,7 +1676,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
continue;
for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
MOE = MI.operands_end();
diff --git a/llvm/lib/CodeGen/LiveRangeShrink.cpp b/llvm/lib/CodeGen/LiveRangeShrink.cpp
index 6c03a87e8d973..054f4370b6090 100644
--- a/llvm/lib/CodeGen/LiveRangeShrink.cpp
+++ b/llvm/lib/CodeGen/LiveRangeShrink.cpp
@@ -130,7 +130,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {
MachineInstr &MI = *Next;
++Next;
- if (MI.isPHI() || MI.isDebugInstr())
+ if (MI.isPHI() || MI.isDebugOrPseudoInstr())
continue;
if (MI.mayStore())
SawStore = true;
@@ -219,7 +219,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
MachineBasicBlock::iterator I = std::next(Insert->getIterator());
// Skip all the PHI and debug instructions.
- while (I != MBB.end() && (I->isPHI() || I->isDebugInstr()))
+ while (I != MBB.end() && (I->isPHI() || I->isDebugOrPseudoInstr()))
I = std::next(I);
if (I == MI.getIterator())
continue;
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index e0ef38dbc72f9..7181dbc9c870a 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -497,7 +497,7 @@ void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
void LiveVariables::runOnInstr(MachineInstr &MI,
SmallVectorImpl<unsigned> &Defs) {
- assert(!MI.isDebugInstr());
+ assert(!MI.isDebugOrPseudoInstr());
// Process all of the operands of the instruction...
unsigned NumOperandsToProcess = MI.getNumOperands();
@@ -572,7 +572,7 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
DistanceMap.clear();
unsigned Dist = 0;
for (MachineInstr &MI : *MBB) {
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
continue;
DistanceMap.insert(std::make_pair(&MI, Dist++));
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index cf22230b510f8..d792ad490487b 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1515,7 +1515,7 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
// Try searching forwards from Before, looking for reads or defs.
const_iterator I(Before);
for (; I != end() && N > 0; ++I) {
- if (I->isDebugInstr())
+ if (I->isDebugOrPseudoInstr())
continue;
--N;
@@ -1553,7 +1553,7 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
do {
--I;
- if (I->isDebugInstr())
+ if (I->isDebugOrPseudoInstr())
continue;
--N;
@@ -1587,7 +1587,7 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
// If all the instructions before this in the block are debug instructions,
// skip over them.
- while (I != begin() && std::prev(I)->isDebugInstr())
+ while (I != begin() && std::prev(I)->isDebugOrPseudoInstr())
--I;
// Did we get to the start of the block?
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 35faceea66760..dd6e3a2dbb9e9 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -297,7 +297,7 @@ priorNonDebug(MachineBasicBlock::const_iterator I,
MachineBasicBlock::const_iterator Beg) {
assert(I != Beg && "reached the top of the region, cannot decrement");
while (--I != Beg) {
- if (!I->isDebugInstr())
+ if (!I->isDebugOrPseudoInstr())
break;
}
return I;
@@ -317,7 +317,7 @@ static MachineBasicBlock::const_iterator
nextIfDebug(MachineBasicBlock::const_iterator I,
MachineBasicBlock::const_iterator End) {
for(; I != End; ++I) {
- if (!I->isDebugInstr())
+ if (!I->isDebugOrPseudoInstr())
break;
}
return I;
@@ -508,7 +508,7 @@ getSchedRegions(MachineBasicBlock *MBB,
MachineInstr &MI = *std::prev(I);
if (isSchedBoundary(&MI, &*MBB, MF, TII))
break;
- if (!MI.isDebugInstr()) {
+ if (!MI.isDebugOrPseudoInstr()) {
// MBB::size() uses instr_iterator to count. Here we need a bundle to
// count as a single instruction.
++NumRegionInstrs;
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 6be9f4e31b49c..41fa3a22c9ce3 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -530,7 +530,7 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
if (!ProcessedBegin)
--I;
- if (MI.isDebugInstr()) {
+ if (MI.isDebugOrPseudoInstr()) {
if (MI.isDebugValue())
ProcessDbgInst(MI);
continue;
@@ -718,7 +718,7 @@ MachineSinking::getBBRegisterPressure(MachineBasicBlock &MBB) {
MIE = MBB.instr_begin();
MII != MIE; --MII) {
MachineInstr &MI = *std::prev(MII);
- if (MI.isDebugValue() || MI.isDebugLabel())
+ if (MI.isDebugValue() || MI.isDebugLabel() || MI.isPseudoProbe())
continue;
RegisterOperands RegOpers;
RegOpers.collect(MI, *TRI, *MRI, false, false);
@@ -1755,7 +1755,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
continue;
}
- if (MI->isDebugInstr())
+ if (MI->isDebugOrPseudoInstr())
continue;
// Do not move any instruction across function call.
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index d377ca66a2d25..c1da51e6f5934 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -1315,8 +1315,9 @@ bool RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
// Abort if the spill cannot be inserted at the MBB' start
MachineBasicBlock *MBB = MF->getBlockNumbered(Number);
if (!MBB->empty() &&
- SlotIndex::isEarlierInstr(LIS->getInstructionIndex(MBB->instr_front()),
- SA->getFirstSplitPoint(Number)))
+ SlotIndex::isEarlierInstr(
+ LIS->getInstructionIndex(*MBB->getFirstNonDebugInstr()),
+ SA->getFirstSplitPoint(Number)))
return false;
// Interference for the live-in value.
if (Intf.first() <= Indexes->getMBBStartIdx(Number))
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 4a20648ec4cea..f535688320b35 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -2962,7 +2962,7 @@ taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
bool JoinVals::usesLanes(const MachineInstr &MI, Register Reg, unsigned SubIdx,
LaneBitmask Lanes) const {
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
return false;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
@@ -3607,7 +3607,7 @@ void RegisterCoalescer::buildVRegToDbgValueMap(MachineFunction &MF)
return MO.isReg() && MO.getReg().isVirtual();
}))
ToInsert.push_back(&MI);
- } else if (!MI.isDebugInstr()) {
+ } else if (!MI.isDebugOrPseudoInstr()) {
CurrentSlot = Slots.getInstructionIndex(MI);
CloseNewDVRange(CurrentSlot);
}
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 8f1fc103e869e..fae1ecfeb738e 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -764,7 +764,7 @@ void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
/// instruction independent of liveness.
void RegPressureTracker::recede(const RegisterOperands &RegOpers,
SmallVectorImpl<RegisterMaskPair> *LiveUses) {
- assert(!CurrPos->isDebugInstr());
+ assert(!CurrPos->isDebugOrPseudoInstr());
// Boost pressure for all dead defs together.
bumpDeadDefs(RegOpers.DeadDefs);
@@ -863,7 +863,7 @@ void RegPressureTracker::recedeSkipDebugValues() {
CurrPos = prev_nodbg(CurrPos, MBB->begin());
SlotIndex SlotIdx;
- if (RequireIntervals && !CurrPos->isDebugInstr())
+ if (RequireIntervals && !CurrPos->isDebugOrPseudoInstr())
SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
// Open the top of the region using slot indexes.
@@ -873,9 +873,9 @@ void RegPressureTracker::recedeSkipDebugValues() {
void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
recedeSkipDebugValues();
- if (CurrPos->isDebugValue()) {
- // It's possible to only have debug_value instructions and hit the start of
- // the block.
+ if (CurrPos->isDebugValue() || CurrPos->isPseudoProbe()) {
+ // It's possible to only have debug_value and pseudo probe instructions and
+ // hit the start of the block.
assert(CurrPos == MBB->begin());
return;
}
@@ -1041,7 +1041,7 @@ static void computeMaxPressureDelta(ArrayRef<unsigned> OldMaxPressureVec,
/// This is intended for speculative queries. It leaves pressure inconsistent
/// with the current position, so must be restored by the caller.
void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
- assert(!MI->isDebugInstr() && "Expect a nondebug instruction.");
+ assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
SlotIndex SlotIdx;
if (RequireIntervals)
@@ -1282,7 +1282,7 @@ LaneBitmask RegPressureTracker::getLiveThroughAt(Register RegUnit,
/// This is intended for speculative queries. It leaves pressure inconsistent
/// with the current position, so must be restored by the caller.
void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
- assert(!MI->isDebugInstr() && "Expect a nondebug instruction.");
+ assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
SlotIndex SlotIdx;
if (RequireIntervals)
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 2ec4915937fac..e35cf7aa69584 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -175,7 +175,7 @@ void RegScavenger::forward() {
I.Restore = nullptr;
}
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
return;
determineKillsAndDefs();
@@ -298,7 +298,7 @@ Register RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
bool inVirtLiveRange = false;
for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
- if (MI->isDebugInstr()) {
+ if (MI->isDebugOrPseudoInstr()) {
++InstrLimit; // Don't count debug instructions
continue;
}
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 5899da777fe95..62948fff86147 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -514,7 +514,7 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
/// TODO: Handle ExitSU "uses" properly.
void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
const MachineInstr *MI = SU->getInstr();
- assert(!MI->isDebugInstr());
+ assert(!MI->isDebugOrPseudoInstr());
const MachineOperand &MO = MI->getOperand(OperIdx);
Register Reg = MO.getReg();
@@ -572,7 +572,7 @@ void ScheduleDAGInstrs::initSUnits() {
SUnits.reserve(NumRegionInstrs);
for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
continue;
SUnit *SU = newSUnit(&MI);
@@ -814,6 +814,9 @@ void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
if (MI.isDebugLabel())
continue;
+ if (MI.isPseudoProbe())
+ continue;
+
SUnit *SU = MISUnitMap[&MI];
assert(SU && "No SUnit mapped to this MI");
@@ -1117,7 +1120,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
// Examine block from end to start...
for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
continue;
// Update liveness. Registers that are defed but not used in this
@@ -1152,7 +1155,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
while (I->isBundledWithSucc())
++I;
do {
- if (!I->isDebugInstr())
+ if (!I->isDebugOrPseudoInstr())
toggleKills(MRI, LiveRegs, *I, true);
--I;
} while (I != Bundle);
diff --git a/llvm/lib/CodeGen/SlotIndexes.cpp b/llvm/lib/CodeGen/SlotIndexes.cpp
index c72bcf2c84df4..c933031ef37db 100644
--- a/llvm/lib/CodeGen/SlotIndexes.cpp
+++ b/llvm/lib/CodeGen/SlotIndexes.cpp
@@ -83,7 +83,7 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) {
SlotIndex blockStartIndex(&indexList.back(), SlotIndex::Slot_Block);
for (MachineInstr &MI : MBB) {
- if (MI.isDebugInstr())
+ if (MI.isDebugOrPseudoInstr())
continue;
// Insert a store index for the instr.
@@ -241,7 +241,7 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
- if (!MI.isDebugInstr() && mi2iMap.find(&MI) == mi2iMap.end())
+ if (!MI.isDebugOrPseudoInstr() && mi2iMap.find(&MI) == mi2iMap.end())
insertMachineInstrInMaps(MI);
}
}
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index d778a9e8c3ef9..597f516a19798 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -819,7 +819,7 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
MachineBasicBlock::iterator MBBI(MI);
bool AtBegin;
do AtBegin = MBBI == MBB->begin();
- while (!AtBegin && (--MBBI)->isDebugInstr());
+ while (!AtBegin && (--MBBI)->isDebugOrPseudoInstr());
LLVM_DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
LIS.removeVRegDefAt(*LI, Def);
diff --git a/llvm/test/Transforms/SampleProfile/pseudo-probe-slotindex.ll b/llvm/test/Transforms/SampleProfile/pseudo-probe-slotindex.ll
new file mode 100644
index 0000000000000..416531836f399
--- /dev/null
+++ b/llvm/test/Transforms/SampleProfile/pseudo-probe-slotindex.ll
@@ -0,0 +1,22 @@
+; REQUIRES: x86_64-linux
+; RUN: llc -print-after=slotindexes -stop-after=slotindexes -mtriple=x86_64-- %s -filetype=asm -o %t 2>&1 | FileCheck %s
+
+define void @foo(i32* %p) {
+ store i32 0, i32* %p
+ call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1)
+ store i32 0, i32* %p
+ ret void
+}
+
+;; Check the pseudo probe instruction isn't assigned a slot index.
+;CHECK: IR Dump {{.*}}
+;CHECK: # Machine code for function foo{{.*}}
+;CHECK: {{[0-9]+}}B bb.0 (%ir-block.0)
+;CHECK: {{[0-9]+}}B %0:gr64 = COPY killed $rdi
+;CHECK: {{^}} PSEUDO_PROBE 5116412291814990879
+;CHECK: {{[0-9]+}}B MOV32mi
+;CHECK: {{[0-9]+}}B RET 0
+
+declare void @llvm.pseudoprobe(i64, i64, i32, i64) #0
+
+attributes #0 = { inaccessiblememonly nounwind willreturn }
\ No newline at end of file
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