[PATCH] D100803: [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 19 15:57:43 PDT 2021


craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll:51
 ; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    addi a3, zero, 5
-; LMULMAX8-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.s.x v0, a3
-; LMULMAX8-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX8-RV32-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
 ; LMULMAX8-RV32-NEXT:    vmv.v.x v25, a2
----------------
This is a regression.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll:56
 define void @gather_const_v2i64(<2 x i64>* %x) {
-; CHECK-LABEL: gather_const_v2i64:
-; CHECK:       # %bb.0:
----------------
grr the script deleted the checks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100803/new/

https://reviews.llvm.org/D100803



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