[PATCH] D100760: [AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D100760#2698969 <https://reviews.llvm.org/D100760#2698969>, @rampitec wrote:

> Is that a functional or performance problem if vcc is used?

It's a correctness problem because when we shrink an instruction like `%4:vgpr_32, %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, %1, 0, implicit $exec` the def of %5 turns into an implicit def of vcc, but we don't touch the uses of %5, so they become uses with no def which fails MIR verification.


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https://reviews.llvm.org/D100760