[PATCH] D100370: [AArch64][SVE] Fix bug in lowering of fixed-length integer vector divides

Mon Apr 19 10:12:04 PDT 2021

paulwalker-arm added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll:1
 ; RUN: llc -aarch64-sve-vector-bits-min=128  -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=16 -check-prefix=NO_SVE
+; RUN: llc -aarch64-sve-vector-bits-min=256  -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=32 -check-prefixes=CHECK,VBITS_EQ_256
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paulwalker-arm wrote:
> Given the updates I wondered if this is still necessary?
Sorry I should have been clearer.  I meant to say that I didn't think **any** of the RUN lines require setting `VBYTES` because with your change the predicate patterns should be fixed based on the `VBITS` prefix in use.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100370/new/

https://reviews.llvm.org/D100370