[PATCH] D100769: [RISCV] Optimize addition with immediate

Ben Shi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 19 08:37:36 PDT 2021


benshi001 created this revision.
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1. simplify the original optimization from customed DAG selection code to TD pattern;
2. optimize i32 addition on riscv64.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100769

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/add-imm.ll

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