[llvm] a02aa91 - [AMDGPU] GCNDPPCombine: simplify API of isShrinkable. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-04-19T14:20:46+01:00
New Revision: a02aa913133c44e29e9a147493ac161b008acce6

URL: https://github.com/llvm/llvm-project/commit/a02aa913133c44e29e9a147493ac161b008acce6
DIFF: https://github.com/llvm/llvm-project/commit/a02aa913133c44e29e9a147493ac161b008acce6.diff

LOG: [AMDGPU] GCNDPPCombine: simplify API of isShrinkable. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index 1a28419e5f0d..53c84639abda 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -99,7 +99,7 @@ class GCNDPPCombine : public MachineFunctionPass {
 
 private:
   int getDPPOp(unsigned Op, bool IsShrinkable) const;
-  bool isShrinkable(MachineInstr &OrigMI, unsigned OrigOp) const;
+  bool isShrinkable(MachineInstr &MI) const;
 };
 
 } // end anonymous namespace
@@ -114,20 +114,21 @@ FunctionPass *llvm::createGCNDPPCombinePass() {
   return new GCNDPPCombine();
 }
 
-bool GCNDPPCombine::isShrinkable(MachineInstr &OrigMI, unsigned OrigOp) const {
-  if (!TII->isVOP3(OrigOp)) {
+bool GCNDPPCombine::isShrinkable(MachineInstr &MI) const {
+  unsigned Op = MI.getOpcode();
+  if (!TII->isVOP3(Op)) {
     return false;
   }
-  if (!TII->hasVALU32BitEncoding(OrigOp)) {
+  if (!TII->hasVALU32BitEncoding(Op)) {
     LLVM_DEBUG(dbgs() << "  Inst hasn't e32 equivalent\n");
     return false;
   }
   // check if other than abs|neg modifiers are set (opsel for example)
   const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
-  if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
-      !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
-      !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0) ||
-      !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)) {
+  if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
+      !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
+      !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) ||
+      !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) {
     LLVM_DEBUG(dbgs() << "  Inst has non-default modifiers\n");
     return false;
   }
@@ -523,7 +524,7 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
       continue;
     }
 
-    bool IsShrinkable = isShrinkable(OrigMI, OrigOp);
+    bool IsShrinkable = isShrinkable(OrigMI);
     if (!(IsShrinkable || TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) {
       LLVM_DEBUG(dbgs() << "  failed: not VOP1/2/3\n");
       break;