[PATCH] D100566: [SCEV] Add a ah-hoc pattern on isImpliedCondBalancedTypes

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 updated this revision to Diff 338484.
jaykang10 added a comment.

Following the comment of @nikic, added checks for negative step and nsw/nuw.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100566/new/

https://reviews.llvm.org/D100566

Files:
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/test/Transforms/IRCE/sibling_loops.ll
  llvm/test/Transforms/IndVarSimplify/lftr-pr20680.ll

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