[PATCH] D100487: [AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll:2-5
+; RUN: llc -aarch64-sve-vector-bits-min=256  < %s | FileCheck %s -D#VBYTES=32  -check-prefixes=CHECK,VBITS_GE_256
+; RUN: llc -aarch64-sve-vector-bits-min=512  < %s | FileCheck %s -D#VBYTES=64  -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_256
+; RUN: llc -aarch64-sve-vector-bits-min=1024 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512,VBITS_GE_256
+; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -D#VBYTES=256 -check-prefixes=CHECK,VBITS_GE_2048,VBITS_GE_1024,VBITS_GE_512,VBITS_GE_256
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Please add `RUN` lines for all the support vector lengths.

Also, just in case somebody wonders why, can you add a comment saying there's no validation for splitting vector operations because the necessary MULH DAG combine does no apply to illegally typed operations.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll:291
+
+; Vector i64 multiplications are not legal for NEON so use SVE when available.
+define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
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Weirdly SVE is not being used here.  Is the output different when SVE is disable?


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll:779
+
+; Vector i64 multiplications are not legal for NEON so use SVE when available.
+define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
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Same comment as smulh_v4i32.


Repository:
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  https://reviews.llvm.org/D100487/new/

https://reviews.llvm.org/D100487