[PATCH] D100435: [ARM] Transforming memset to Tail predicated Loop

[Malhar via Phabricator via llvm-commits]

malharJ marked an inline comment as done.
malharJ added inline comments.


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Comment at: llvm/test/CodeGen/Thumb2/mve-phireg.ll:206
+; CHECK-NEXT:  .LBB1_1: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vldrw.u32 q0, [sp] @ 16-byte Reload
+; CHECK-NEXT:    vstrb.8 q0, [r2], #16
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@dmgreen , 

This seems to be happening because of a 16-byte spill ( line 169 ).

And it's being generated after I updated the code to create the VDUP in
 EmitTargetCodeForMemset() instead of during the MIR level transform.

I'm not sure why the spill is happening (not really familiar with RA), but do you
 think it's worth investigating ? It doesnt seem to happen in the simpler tests. 
 


Repository:
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  https://reviews.llvm.org/D100435/new/

https://reviews.llvm.org/D100435