[llvm] 37a4621 - [DAG] SelectionDAG::isSplatValue - early out if binop is not splat. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 16 10:26:41 PDT 2021
Author: Simon Pilgrim
Date: 2021-04-16T18:26:33+01:00
New Revision: 37a4621fb6ffc121ec78936a8243219ff53be760
URL: https://github.com/llvm/llvm-project/commit/37a4621fb6ffc121ec78936a8243219ff53be760
DIFF: https://github.com/llvm/llvm-project/commit/37a4621fb6ffc121ec78936a8243219ff53be760.diff
LOG: [DAG] SelectionDAG::isSplatValue - early out if binop is not splat. NFCI.
Just return false if we fail to match splats - the remainder of the code is for (fixed)vector operations - shuffles/insertions etc.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 71964b3de2b0..d24455572273 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2472,7 +2472,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
return true;
case ISD::ADD:
case ISD::SUB:
- case ISD::AND:
+ case ISD::AND:
case ISD::XOR:
case ISD::OR: {
APInt UndefLHS, UndefRHS;
@@ -2483,7 +2483,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
UndefElts = UndefLHS | UndefRHS;
return true;
}
- break;
+ return false;
}
case ISD::ABS:
case ISD::TRUNCATE:
More information about the llvm-commits
mailing list