[PATCH] D100487: [AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 338074.
bsmith marked 5 inline comments as done.
bsmith edited the summary of this revision.
bsmith added a comment.

- Rename ISD nodes to match common names
- Preserve some alphabetical ordering
- Fix 2048 vector width tests
- Update fixed width tests to test vector widths smaller than the given value
- Allow generation of SVE mulh instructions for neon sized i64 vectors
- Add test to check divide expansion that can now happen
- Add minsize attribute to some SVE divide tests to prevent divide expansion from happening


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100487/new/

https://reviews.llvm.org/D100487

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-expand-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
  llvm/test/CodeGen/AArch64/sve-int-mulh-pred.ll
  llvm/test/CodeGen/AArch64/sve2-int-mulh.ll

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