[llvm] 394eb91 - [NFC][AArch64][SVE] Move select-sve.ll tests to sve-select.ll
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 16 04:00:53 PDT 2021
Author: Caroline Concatto
Date: 2021-04-16T11:59:53+01:00
New Revision: 394eb91854fe117c97ece9ae31fb699cf8776708
URL: https://github.com/llvm/llvm-project/commit/394eb91854fe117c97ece9ae31fb699cf8776708
DIFF: https://github.com/llvm/llvm-project/commit/394eb91854fe117c97ece9ae31fb699cf8776708.diff
LOG: [NFC][AArch64][SVE] Move select-sve.ll tests to sve-select.ll
This patch merges the two select tests: select-sve.ll and sve-select.ll into
sve-select.ll as they are both testing SELECT instruction
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-select.ll
Removed:
llvm/test/CodeGen/AArch64/select-sve.ll
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/select-sve.ll b/llvm/test/CodeGen/AArch64/select-sve.ll
deleted file mode 100644
index b0959d215161..000000000000
--- a/llvm/test/CodeGen/AArch64/select-sve.ll
+++ /dev/null
@@ -1,134 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
-
-define <vscale x 16 x i8> @select_nxv16i8(i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: select_nxv16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p0.b, xzr, x8
-; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
- ret <vscale x 16 x i8> %res
-}
-
-define <vscale x 8 x i16> @select_nxv8i16(i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: select_nxv8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p0.h, xzr, x8
-; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
- ret <vscale x 8 x i16> %res
-}
-
-define <vscale x 4 x i32> @select_nxv4i32(i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: select_nxv4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p0.s, xzr, x8
-; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
- ret <vscale x 4 x i32> %res
-}
-
-define <vscale x 2 x i64> @select_nxv2i64(i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: select_nxv2i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p0.d, xzr, x8
-; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
- ret <vscale x 2 x i64> %res
-}
-
-define <vscale x 8 x half> @select_nxv8f16(i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: select_nxv8f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p0.h, xzr, x8
-; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b
- ret <vscale x 8 x half> %res
-}
-
-define <vscale x 4 x float> @select_nxv4f32(i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: select_nxv4f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p0.s, xzr, x8
-; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
- ret <vscale x 4 x float> %res
-}
-
-define <vscale x 2 x double> @select_nxv2f64(i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: select_nxv2f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p0.d, xzr, x8
-; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b
- ret <vscale x 2 x double> %res
-}
-
-define <vscale x 16 x i1> @select_nxv16i1(i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
-; CHECK-LABEL: select_nxv16i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p2.b, xzr, x8
-; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b
- ret <vscale x 16 x i1> %res
-}
-
-define <vscale x 8 x i1> @select_nxv8i1(i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
-; CHECK-LABEL: select_nxv8i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p2.h, xzr, x8
-; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b
- ret <vscale x 8 x i1> %res
-}
-
-define <vscale x 4 x i1> @select_nxv4i1(i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
-; CHECK-LABEL: select_nxv4i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p2.s, xzr, x8
-; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b
- ret <vscale x 4 x i1> %res
-}
-
-define <vscale x 2 x i1> @select_nxv2i1(i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
-; CHECK-LABEL: select_nxv2i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sbfx x8, x0, #0, #1
-; CHECK-NEXT: whilelo p2.d, xzr, x8
-; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
-; CHECK-NEXT: ret
- %res = select i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b
- ret <vscale x 2 x i1> %res
-}
diff --git a/llvm/test/CodeGen/AArch64/sve-select.ll b/llvm/test/CodeGen/AArch64/sve-select.ll
index 2d2ea47ae359..bbc879c34985 100644
--- a/llvm/test/CodeGen/AArch64/sve-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-select.ll
@@ -1,4 +1,137 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 16 x i8> @select_nxv16i8(i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: select_nxv16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.b, xzr, x8
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
+ ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @select_nxv8i16(i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: select_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.h, xzr, x8
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
+ ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @select_nxv4i32(i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: select_nxv4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.s, xzr, x8
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @select_nxv2i64(i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: select_nxv2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.d, xzr, x8
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 8 x half> @select_nxv8f16(i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: select_nxv8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.h, xzr, x8
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @select_nxv4f32(i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: select_nxv4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.s, xzr, x8
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @select_nxv2f64(i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: select_nxv2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.d, xzr, x8
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b
+ ret <vscale x 2 x double> %res
+}
+
+define <vscale x 16 x i1> @select_nxv16i1(i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: select_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.b, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @select_nxv8i1(i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: select_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.h, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @select_nxv4i1(i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: select_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.s, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @select_nxv2i1(i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: select_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.d, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b
+ ret <vscale x 2 x i1> %res
+}
; Integer vector select
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