[llvm] ec0f7c6 - [RISCV] Rerun stack test through update_llc_test_checks.py

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2021-04-16T11:08:58+01:00
New Revision: ec0f7c6923c1e6a722be6f4e0bb0e3d08b3bc3b1

URL: https://github.com/llvm/llvm-project/commit/ec0f7c6923c1e6a722be6f4e0bb0e3d08b3bc3b1
DIFF: https://github.com/llvm/llvm-project/commit/ec0f7c6923c1e6a722be6f4e0bb0e3d08b3bc3b1.diff

LOG: [RISCV] Rerun stack test through update_llc_test_checks.py

Adjusts formatting of comments only. Just to reduce diffs in future
patches.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
index 67beafdade6da..a00b85cc2dff2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
@@ -158,8 +158,8 @@ define void @lmul4_and_1() nounwind {
 ; CHECK-LABEL: lmul4_and_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -32
-; CHECK-NEXT:    sd ra, 24(sp)  # 8-byte Folded Spill
-; CHECK-NEXT:    sd s0, 16(sp)  # 8-byte Folded Spill
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 32
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    addi a1, zero, 5
@@ -167,8 +167,8 @@ define void @lmul4_and_1() nounwind {
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -32
-; CHECK-NEXT:    ld s0, 16(sp)  # 8-byte Folded Reload
-; CHECK-NEXT:    ld ra, 24(sp)  # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 4 x i64>
@@ -180,8 +180,8 @@ define void @lmul4_and_2() nounwind {
 ; CHECK-LABEL: lmul4_and_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -32
-; CHECK-NEXT:    sd ra, 24(sp)  # 8-byte Folded Spill
-; CHECK-NEXT:    sd s0, 16(sp)  # 8-byte Folded Spill
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 32
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    addi a1, zero, 6
@@ -189,8 +189,8 @@ define void @lmul4_and_2() nounwind {
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -32
-; CHECK-NEXT:    ld s0, 16(sp)  # 8-byte Folded Reload
-; CHECK-NEXT:    ld ra, 24(sp)  # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 4 x i64>