[PATCH] D98479: [RISCV] Add DAG combine to optimize vXi64 all ones/zeros fixed vector on RV32.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Sorry for dropping the ball on this. I still haven't managed to look into it further. Is this a pattern that only shows up for all-zeros/all-ones, or is that the only cases that this patch is interested in?

Just wondering: instead of generating this bitcast/v2Xi32 pattern, could we lower this to `SPLAT_VECTOR_PARTS` and teach LLVM about this node a little better where required? I feel like the last discussion I read was that SPLATs should be open to fixed-length vectors too. That would at least keep it generic for a little longer, and catch all kinds of splat rather than just ones and zeros.

I'm happy to look into this further if you think it's worthwhile. It doesn't have to hold up this patch.


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https://reviews.llvm.org/D98479