[PATCH] D100026: [X86] Support AMX fast register allocation

[Xiang Zhang via Phabricator via llvm-commits]

xiangzhangllvm marked 12 inline comments as done.
xiangzhangllvm added a comment.

The patch is big, thanks for Pengfei's review!



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Comment at: llvm/lib/Target/X86/X86PreAMXConfig.cpp:356
+    // Prepare for fast register allocation at O0.
+    if (TM->getOptLevel() == CodeGenOpt::None) {
+
----------------
pengfei wrote:
> Do we need to check it since the pass is only created under O0?
it checked at its caller.


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Comment at: llvm/lib/Target/X86/X86PreAMXConfig.cpp:216
+
+  // The def of KeyAMX should be stored.
+  // Todo: is it key amx can be no def?
----------------
pengfei wrote:
> Why can't be DPSSD etc.?
// here "be stored" means "be stored into mem" not "be TileStore instruction", I'll refine this comments.


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Comment at: llvm/test/CodeGen/X86/AMX/amx-fast-tile-config.mir:31
+    %16 = bitcast <16 x i32>* %6 to i8*
+    store <16 x i32> zeroinitializer, <16 x i32>* %6, align 64
+    %amx.tmm.0.shape.row1 = getelementptr i8, i8* %16, i64 48
----------------
xiangzhangllvm wrote:
> pengfei wrote:
> > But the alignment of store and alloca is not match. You may cause runtime crush due the the alignment.
> Make sense, thanks!
updated in other tests, e.g. llvm/test/CodeGen/X86/AMX/amx-configO2toO0-precfg.ll  : line 30


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100026/new/

https://reviews.llvm.org/D100026