[PATCH] D100574: [RISCV][WIP] Fix missing emergency slots for scalable stack offsets

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

Sorry for not upstreaming this fix when I found it. I am busy on testing/debugging our downstream version recently. I think you need to update several tests after we reserved two more scavenging slots.

The tests we have updated are

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/load-store-scalable-struct.ll
llvm/test/CodeGen/RISCV/rvv/localvar.ll
llvm/test/CodeGen/RISCV/rvv/memory-args.ll
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100574/new/

https://reviews.llvm.org/D100574