[PATCH] D100026: [X86] Support AMX fast register allocation

[Xiang Zhang via Phabricator via llvm-commits]

xiangzhangllvm added inline comments.


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Comment at: llvm/test/CodeGen/X86/AMX/amx-fast-tile-config.mir:31
+    %16 = bitcast <16 x i32>* %6 to i8*
+    store <16 x i32> zeroinitializer, <16 x i32>* %6, align 64
+    %amx.tmm.0.shape.row1 = getelementptr i8, i8* %16, i64 48
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pengfei wrote:
> But the alignment of store and alloca is not match. You may cause runtime crush due the the alignment.
Make sense, thanks!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100026/new/

https://reviews.llvm.org/D100026