[PATCH] D100398: [AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp:477
+    return false;
+  case Intrinsic::aarch64_neon_uaddlv:
+    return true;
----------------
paquette wrote:
> aemerson wrote:
> > Can we look up this information using the type signature of the intrinsic instead of hard coding it?
> Maybe I'm looking in the wrong place, but it looks like probably not:
> 
> ```
>   class AdvSIMD_1VectorArg_Int_Across_Intrinsic
>     : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
>   ...
>   def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
> ```
> 
> 
> 
In that case, this intrinsic could define a GPR right? The comment for this function says it's true if the ID only uses and defines FPRs.


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  https://reviews.llvm.org/D100398/new/

https://reviews.llvm.org/D100398