[llvm] 2806781 - [Hexagon] Avoid infinite loops in type legalization when lowering SETCC

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2021-04-15T13:34:37-05:00
New Revision: 280678122d3175943e41310d56a17924ea38ffc1

URL: https://github.com/llvm/llvm-project/commit/280678122d3175943e41310d56a17924ea38ffc1
DIFF: https://github.com/llvm/llvm-project/commit/280678122d3175943e41310d56a17924ea38ffc1.diff

LOG: [Hexagon] Avoid infinite loops in type legalization when lowering SETCC

Only widen SETCC if the operands can be widened. Not checking that caused
infinite widen-split loops in legalization.

Added: 
    llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 29b75814da6e9..e7d3c7c24f348 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1954,6 +1954,8 @@ HexagonTargetLowering::WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
   unsigned WideOpLen = (8 * HwLen) / ElemTy.getSizeInBits();
   assert(WideOpLen * ElemTy.getSizeInBits() == 8 * HwLen);
   MVT WideOpTy = MVT::getVectorVT(ElemTy, WideOpLen);
+  if (!Subtarget.isHVXVectorType(WideOpTy, true))
+    return SDValue();
 
   SDValue WideOp0 = appendUndef(Op0, WideOpTy, DAG);
   SDValue WideOp1 = appendUndef(Op1, WideOpTy, DAG);

diff  --git a/llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll b/llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll
new file mode 100644
index 0000000000000..1798654975e55
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that we scalarize the comparison. This testcase used to loop forever
+; due to the repeated split-widen operations in legalizing SETCC.
+
+; CHECK: fred:
+; CHECK: sfcmp.gt
+; CHECK: vinsert
+
+define <32 x i32> @fred(<32 x i32> %a0, <32 x i32> %a1) #0 {
+b0:
+  %v0 = bitcast <32 x i32> %a0 to <32 x float>
+  %v1 = bitcast <32 x i32> %a1 to <32 x float>
+  %v2 = fcmp ogt <32 x float> %v0, %v1
+  %v3 = select <32 x i1> %v2, <32 x float> zeroinitializer, <32 x float> %v0
+  %v4 = bitcast <32 x float> %v3 to <32 x i32>
+  ret <32 x i32> %v4
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length128b" }